講員: Prof. David Brooks

講題:Research Infrastructure for Accelerator-Centric SoC
       Architectures

時間:104/1/20(二) 13:30-16:30

地點:台達館地下一樓 璟德講堂

報名網址:http://goo.gl/forms/CWMMb1Egp5   

報名時間:即日起至104/1/16止。

講員簡介:

David Brooks is the Haley Family Professor of Computer Science in the School of Engineering and Applied Sciences at Harvard University. Prior to joining Harvard, he was a research staff member at IBM T.J. Watson Research Center.  Prof. Brooks received his BS in Electrical Engineering at the University of Southern California and MA and PhD degrees in Electrical Engineering at Princeton University.  His research interests include resilient and power-efficient computer hardware and software design for high-performance and embedded systems. Prof. Brooks has received several honors and awards including the 2012 ACM Maurice Wilkes Award, NSF CAREER award, IBM Faculty Partnership Award, and DARPA Young Faculty Award.

摘要:

Hardware acceleration in the form of customized datapath and control circuitry tuned to specific applications has gained popularity for its promise to utilize transistors more efficiently. Historically, the computer architecture community has focused on the design of general-purpose processors and graphics processors (GPUs). Research infrastructure to study such designs is extensive, including analytical performance models, workload characterization approaches, detailed microarchitectural simulators, power/energy models, and design flows to enable architecture research. Envisioning future computing systems with a diverse set of general-purpose cores and accelerators, researchers must add accelerator-based research infrastructures to their toolboxes to be better equipped to explore the future heterogeneous, accelerator-centric 

This tutorial discusses state-of-the-art research infrastructure available for accelerator computing research. The tutorial is split into pre-RTL and post-RTL modeling and design.  Accelerators are typically designed using standard ASIC design flow including RTL generation, simulation, and synthesis. However, RTL flows are necessarily low-level and relying exclusively on such flows inhibits architectural research. The first half of the tutorial describes higher level modeling tools and techniques. The tutorial will introduce an ISA-independent workload characterization approach to understand workload behavior before designing accelerators. This will be followed by a detailed discussion of Aladdin, a pre-RTL, power-performance simulation framework to facilitate architects to rapidly explore the design space of accelerators. Recent advances in high-level synthesis (HLS) tools provide a promising path for accelerator development in the future, and the tutorial will describe the capabilities of commercial tools like Xilinx's Vivado HLS.