Tutorial Date: April 30, Thursday, am 9-12, Time: 3 hours

Presenter: Professor Fernando Silveira,Universidad de la Republica, Uruguay

Title: Intuitive and power optimized analog and RF CMOS design based on gm/ID and drain current density

Location: 資電館R447

Registration:  http://dtc.web.nthu.edu.tw/files/87-1008-1489.php

Deadline:  April 27, Monday

Abstract:

This lecture addresses transistor level design of analog and RF CMOS circuits. First, the design methodology based on the trans conductance to current ratio (gm/ID) and the drain current density is reviewed [1, 2]. It is shown the role of gm/ID ratio as a key variable with variation in a small range that allows to efficiently explore the MOS transistor design space in all regions of inversion (weak, moderate and strong) and to select the size and bias point, while considering the trade-offs regarding power – bandwidth – precision (matching, gain) – signal range and noise. The result is a very didactic approach to CMOS analog and RF design that allows minimizing the trial and error iterations on the design by giving the designer a clear view on how to move in the design space. This quality made that the method has been adopted in various universities worldwide. The key relationship applied for the design (between gm/ID and current density) can be obtained from analytical models, simulation or measurements, making the approach particularly suitable for nanometer and non-standard technologies where an analytical model is complex or unavailable. The lecture is illustrated with the design and power optimization of analog and RF circuits(amplifiers,  LNA [3], VCO [4], PA) in technologies down to below 100nm channel length and post-CMOS devices ([5]) applying this method.

1.F. Silveira, D. Flandre, P.G.A. Jespers, "A gm/ID Based Methodology for the Design of CMOS Analog Circuits and its Application to the Synthesis of a Silicon-on-Insulator Micropower OTA", IEEE Journal of Solid State Circuits, Vol. 31, No. 9, Sept. 1996, pp.1314 – 1319.2.P.G.A. Jespers, “The gm/ID Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits”, Springer 2010.3.R. Fiorelli, F. Silveira, E. Peralias, “MOST moderate-weak-inversion region as the optimum design zone for CMOS 2.4-GHz CS-LNAs”, IEEE Transactions on Microwave Theory and Techniques, Vol 62, pp. 556-566, 20144.R. Fiorelli, E. Peralias, F. Silveira,  “LC-VCO Design Optimization Methodology Based on the gm/ID Ratio for Nanometer CMOS Technologies”, IEEE Transactions on Microwave Theory and Techniques, Vol 59, Issue 7,  pp. 1822-1831, 20115.B. Sensale-Rodriguez et al, Perspectives of TFETs for low power analog ICs, Subthreshold Microelectronics Conference (Sub VT), 2012 IEEE.

About the presenter:

Fernando Silveira received the Electrical Engineering degree from Universidad de la Republica, Uruguay in 1990 and the MSc. and PhD degree in Microelectronics from Universite catholique de Louvain, Belgium in, respectively, 1995 and 2002. He is Professor at Universidad de la Republica, Uruguay, where he is currently the Head of the Electrical Engineering Department. His research interests are in design of ultra-low-power analog and RF integrated circuits and systems, in particular with biomedical application. In this field, he is co-author of one book and many technical articles and advised Masters and PhD thesis. He has acted as invited plenary speaker at various events and served as reviewer and member of the TPC of several journals and conferences.

He has multiple industrial activities with CCC Medical Devices and Nano WattICs, including leading the design of an ASIC for implantable pacemakers, applied in industrial production and designing analog circuit modules for implantable devices for various companies worldwide (USA, Israel, Europe and Canada) that are part of medical devices which are currently on the market or under human clinical evaluation, mainly related to the cardiovascular and neural fields. Dr. Silveira received the “Distinguished Engineer” award by the Uruguayan Association of Engineers in 2007 and was a member for 2011-2012 of the Distinguished Lecturers Program of the IEEE Circuits and Systems Society.