DTC, Design Technology Center

Tutorial Date: April 30, Thursday, 13:30pm-15:00pm, Time: 90 min
Presenter: Dr. Wu-Tung Cheng, Chief Scientist & Director of Advanced Test Research Mentor Graphics Corporation

Title: Identify Problematic Layout Patterns

        Through Volume Diagnosis

Location: 資電館R447 

Registration: http://dtc.web.nthu.edu.tw/files/87-1008-34.php

Deadline:  April 28, Tuesday

Abstract:

Due to various manufacture difficulties in nano-scale semiconductor devices, certain layout patterns cannot be manufactured properly and cause significant yield loss. Due to the time needed to run through complete lithography simulation, it may not be possible to identify all of them before silicon manufacture. Currently, human experience is needed to group several defects found from physical failure analysis to identify problematic layout patterns. However, the whole process is very time-consuming. To speed-up yield ramp-up, we proposed to automatically identify problematic layout patterns by analyzing data from volume diagnosis. First, responses from failing devices are analyzed using defect diagnosis tools. Next the results of diagnoses are analyzed using statistical, data mining and machine learning techniques to effectively determine the underlying problematic layout patterns. In this presentation, we will discuss the procedures and statistics methods for analyzing diagnosis data and put special attention to the link between defects and layout patterns.

About the presenter:

Dr. Wu-Tung Cheng received the B.S. and M.S. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 1978 and 1982, respectively, and the Ph.D. degree in computer science from the University of Illinois at Urbana–Champaign, Urbana, IL, in 1985. From 1985 to 1990, he was with AT&T Bell Laboratories, Princeton, NJ, developing a test pattern generation system for digital circuits. From 1990 to 1993, he was a cofounder of CheckLogic System, Inc., and was the Vice President of Engineering, leading a team to develop commercial automatic test-generation products, which included FastScan, FlexTest, and DFTAdvisor. In 1993, CheckLogic was merged with Mentor Graphics Corporation, Wilsonville, OR. Since then, he has had various technical and management positions in design for test area at Mentor Graphics Corporation. He is currently a Chief Scientist and the director of Advanced Test Research, leading a team to develop new design-for-test solutions for future semiconductor quality and yield issues. He has published over 120 research papers in these areas and is the Coinventor of 30 patents. Dr. Cheng serves as a member of several technical program committees of workshops and conferences.